The present invention relates to a method for manufacturing a VLSI semiconductor device, and particularly to a method for manufacturing a VLSI semiconductor device with the density of 16M DRAMs or greater.
Along with higher packing density and miniaturization which requires processing techniques on a 0.5 .mu.m design rule, 16M DRAM devices demand reliability and performance improvements. In consideration of reliability, a supply voltage of 3.3 V is used instead of using 5 V, providing decreased gate oxide film failure rate and improved time-dependent dielectric breakdown characteristics. And, for improving performance, it is necessary to boost the word line voltage for driving the access transistors of the cell array. For high speed operation, a technique is needed which allows a gate insulating layer of a periphery circuit's transistor to be thinner than before.
The desired case is to optimize characteristics and performance between transistors in the cell array and transistors in the peripheral circuitry. Generally, in a conventional DRAM process, a cell transistor of the cell array and a peripheral transistor of the peripheral circuit section are formed at the same time, with the cell capacitor being formed later. Accordingly, the close interdependence between the cell transistor and the peripheral transistor in the manufacturing process is followed by many restrictions in the improvements to the characteristics of each.
Moreover, since the cell transistor and the peripheral transistor are simultaneously formed on the wafer and, then, the capacitor is formed in the cell array, an impurity implanted into the silicon is diffused by the heat treatment performed during the formation of the capacitor. Thus, shallow junctions in the peripheral transistor are difficult, and the succeeding heat treatment degrades transistor's performance and reliability. Especially susceptible to the heat treatment are dopants such as boron (B) or boron difluoride (BF.sub.2) which are used to adjust the threshold voltage of a PMOS transistor, forming a deep junction and lowering the breakdown voltage of the PMOS transistor.